This invention relates generally to spatial light modulator displays.
A projection display system typically includes one or more spatial light modulators (SLMs) that modulate light for purposes of producing a projected image. The SLM may include, for example, a liquid crystal display (LCD) such as a high temperature polysilicon (HTPS) LCD panel or a liquid crystal on silicon (LCOS) microdisplay, a grating light valve or a MEMs (where “MEMs” stands for micro-electro-mechanical devices) light modulator such as a digital mirror display (DMD) to modulate light that originates from a lamp of the projection display system. In typical projection display systems, the lamp output is formatted with optics to deliver a uniform illumination level on the surface of the SLM. The SLM forms a pictorial image by modulating the illumination into spatially distinct tones ranging from dark to bright based on supplied video data. Additional optics then relay and magnify the modulated illumination pattern onto a screen for viewing.
The SLM typically includes an array of pixel cells, each of which is electrically controllable to establish the intensity of a pixel of the projected image. In some projection display systems, SLMs are transmissive and in others, they are reflective. For the purposes of simplification, the discussion will address reflective SLMs. An SLM may be operated so that each pixel has only two states: a default reflective state which causes either a bright or a dark projected pixel and a non-default reflective state which causes the opposite projected pixel intensity. In the case of an LCOS SLM, the pre-alignment orientation of the LC material and any retarders in the system determine whether the default reflective state is normally bright or normally dark. For the purposes of simplification, the discussion will denote the default reflective state as normally bright, i.e., one in which the pixel cell reflects incident light into the projection lens (the light that forms the projected image) to form a corresponding bright pixel of the projected image. Thus, in its basic operation, the pixel cell may be digitally-controlled to form either a dark pixel (in its non-default reflective state) or a bright pixel (in its default reflective state). In the case of a DLP SLM, the states may represent the pixel in a co-planar position to the underlying substrate.
Although its pixels are operated digitally, the above-described SLM may also be used in an application to produce visually perceived pixel intensities (called “gray scale intensities”) between the dark and bright levels. For such an application, each pixel may be controlled by pulse width modulation (PWM), a control scheme that causes the human eye to perceive gray scale intensities in the projected image, although each pixel cell still only assumes one of two states at any one time. The human visual system perceives a temporal average of pixel intensity when the PWM control operates at sufficiently fast rates.
In the PWM control scheme, a pixel intensity (or tone) is established by controlling the time that the pixel cell stays in its reflective state and the time that the pixel cell remains in the non-reflective state during an interval time called a PWM cycle. This type of control is also referred to as duty cycle control in that the duty cycle (the ratio of the time that the pixel cell is in its reflective state to the total time the pixel cell is in its non-reflective and reflective states) of each PWM cycle is controlled to set the pixel intensity. A relatively bright pixel intensity is created by having the pixel cell spend a predominant proportion of time in its reflective state during the PWM cycle, while a relatively dark pixel intensity is created by having the pixel cell spend a predominant amount of time in its non-reflective state during the PWM cycle.
The quality of the projected image typically is a function of the number of possible gray scale intensities, also called the “bit depth.” For the above-described PWM control scheme, a bit depth of “N” means that the PWM cycle is divided into 2N time consecutive and non-overlapping time segments. For a particular PWM cycle, each of the time segments in which the pixel cell is in its reflective state contributes to the overall luminance of the corresponding pixel. Each time segment of the PWM cycle typically corresponds in duration to the cycle of a clock signal. Thus, the larger the number of time segments (i.e., the greater the number of gray scale intensities), the higher the frequency of this clock signal, thereby requiring a high speed clock to form the pixel gray scale or tonal range. Power consumption is also a function of this clock frequency and also increases with bit depth.
Other factors may increase the clock rate needed for a particular bit depth. For example, for a three SLM LCD panel projection system (one SLM for each primary color), the PWM cycle may have a period that is equal to one half of the video data's field time (typically 1/60 second). Opposite drive voltage polarities are needed in LCD systems to prevent voltage bias accumulation. This is well known for liquid crystal display systems. Thus, LCD SLM devices require two PWM cycles in each video data field. This doubles the clock rate requirement.
For a two SLM panel projection system where one of the SLM panels is temporally shared by two primary colors, the video frame time must be split to allocate PWM cycles to each primary color, thereby increasing the needed PWM clock rate if the same bit depth is maintained in all colors.
For a one SLM panel projection system with an SLM panel temporally shared by all three primary colors, the video frame time must be further subdivided. For an LCOS SLM the video frame time would be divided into six PWM cycles, a pair for each primary color. The PWM clock period may have an even shorter duration when the unequal length PWM cycles are needed to adjust the display white point. Since common projection lamps are rich in blue and weak in red output, it is generally necessary to devote longer portions of the video frame time to red to achieve white balance. This necessitates the PWM clock period to be increasingly small and the clock frequently and power consumption to be increasingly high.